1. Technical Field
The present application relates to processes for forming integrated circuit devices and, more particularly, to processes for forming integrated circuit devices having a memory array.
2. Related Art
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. However, there are many problems that result from scaling down such circuitry.
Semiconductor manufacturing includes front-end processing, which includes processes for forming transistors on a wafer. For example, the front-end processing can include processes for forming vertical channels. Various processes have been successful in reducing the pitch of such structures, allowing for scaling down the structures formed during front-end processing.
Semiconductor manufacturing also includes a back-end processing of wafer fabrication. The back-end processing is also referred to as back end of line (BEOL), and usually includes creating metal interconnects for interconnecting transistors formed during the front-end processing. The back-end processing can also include formation of insulating structures between the metal interconnects.
While various processes have been successful in scaling down the structures formed during front-end processing, such processes have not been as successful for scaling down the structures formed during back-end processing. For example, while processes are known for successfully scaling down the pitch of vertical channels formed during front-end processing, such processes are not as useful for scaling down of the back-end pitch of contact and metal structures. Thus, the inability to scale down back-end structures limits the overall ability to scale down an integrated circuit device.
This may include the width and spacing of interconnecting lines and the surface geometry such as corners and edges of various features.
Thus, it is desirable to find new approaches for the manufacturing of integrated circuits in order to allow for desired scaling, particularly of metal and contact structures formed during back-end processing.